[sv-ec] Confusing packed struct assignment rules in LRM

Committee,
 
Please forgive me if this is directed to the wrong committee.  I am
reading the LRM and find section 6.7 somewhat confusing.  The confusion
arises from mostly the examples.  The text is pretty clear as it says
its "an error to have a packed ....".  I interpret this to mean either
by struct member or by bit reference.  However the first set of examples
seems to suggest otherwise if the reader sees them as a collective
example rather than discrete examples taken on their own.  The next set
of illegal examples I believe are to be read as a set.  Meaning you
can't do both assign types together.  Perhaps this has already been
address, if so my apologies for raising the question.
 
=== Text Snippet from the LRM =====
SystemVerilog variables can be packed or unpacked aggregates of other
types. Multiple assignments made
to independent elements of a variable are examined individually. An
assignment where the left-hand side
contains a slice is treated as a single assignment to the entire slice.
It shall be an error to have a packed structure
or array type written with a mixture of procedural and continuous
assignments. Thus, an unpacked
structure or array can have one element assigned procedurally and
another element assigned continuously.
And, elements of a packed structure or array can be assigned with
multiple continuous assignments, provided
that each bit is covered by no more than a single continuous assignment.
For example, assume the following
structure declaration:
struct {
  bit [7:0] A;
  bit [7:0] B;
  byte C;
} abc;
 
The following statements are legal assignments to struct abc:
assign abc.C = sel ? 8'hBE : 8'hEF;
not (abc.A[0],abc.B[0]),
(abc.A[1],abc.B[1]),
(abc.A[2],abc.B[2]),
(abc.A[3],abc.B[3]);
always @(posedge clk) abc.B <= abc.B + 1;
 
The following additional statements are illegal assignments to struct
abc:
// Multiple continuous assignments to abc.C
assign abc.C = sel ? 8'hDE : 8'hED;
// Mixing continuous and procedural assignments to abc.A
always @(posedge clk) abc.A[7:4] <= !abc.B[7:4];
=====================================================
Bryan Bullis                 
ASIC Design Engineer        phone: (919) 392-3013   
Router Technology Group     fax:   (919) 392-4537    
Cisco Systems, Inc.         email: bbullis@cisco.com
 

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