RE: [sv-ec] why classes are skipped in name space definition in SV LRM

Your examples need "endmodule" changed to "endclass" in a couple of
cases.

The namespace descriptions are not very rigorous.

From an implementation viewpoint, if we need to be able to distinguish
whether a name is a module/program/interface versus a type name, based
on the syntactic context, I don't think there is any difference whether
these are inside a module or not.


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>From: "danielm" <danielm@aldec.com.pl>
>To: "'Bresticker, Shalom'" <shalom.bresticker@intel.com>, <sv-ec@eda.org>
>Subject: RE: [sv-ec] why classes are skipped in name space definition in SV LRM
>Date: Wed, 22 Aug 2007 13:29:26 +0200
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>X-Received: By mx-sanjose2.Cadence.COM as l7MBRctH029839 at Wed Aug 22 04:27:38 
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>
>Thanks for yours reply,
> 
>So both codes I've proposed in my 1st email should compile - because module
>name is in definition name space, and user-defined name is in compilation
>unit scope?
> 
>But what seems inconsistent for me is that module name space is common for
>nested module and nested user-defined types (oposite to compilation unit
>space and definition space). 
> 
>Regarding to 19.3 e below code is illegal:
>  module top;
>    module a;
>    endmodule
>    class a;
>    endmodule
>  endmodule
> 
>while below is legal
>    module a;
>    endmodule
>    class a;
>    endmodule
> 
>am I correct?
> 
>DANiel
>
>  _____  
>
>From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
>Sent: Wednesday, August 22, 2007 11:49 AM
>To: danielm; sv-ec@server.eda.org
>Subject: RE: [sv-ec] why classes are skipped in name space definition in SV
>LRM
>
>
>Type names defined with typedef are included in what is called in 19.13 (of
>1800-2005) "user-defined types".
> 
>Classes are also considered to be a user-defined type.
> 
>I personally think this should be more explicit.
> 
>See more on this in Mantis 1847: http://www.eda.org/mantis/view.php?id=1847
> 
>Shalom
>
>
>  _____  
>
>From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
>Behalf Of danielm
>Sent: Wednesday, August 22, 2007 12:06 PM
>To: sv-ec@server.eda.org
>Subject: [sv-ec] why classes are skipped in name space definition in SV LRM
>
>
>LRM chapter 19.13. Name spaces - says nothing about classes (and type names
>defined with typedef). It was forgotten to add rules for classes here or
>classes are skiiped on purpose.
> 
>I'm not sure if class name is in the same space like module name?
> 
>
>Is below code it legal or not?
>  class a;
>   int b;
>  endclass
>
>  typedef a A;
>
>  module a ();
>   A v;
>  endmodule
> 
>Same question about typedef:
>typedef int a;
>module a;
>endmodule
> 
> 
>DANiel
> 
>
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Steven Sharp
sharp@cadence.com


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