[sv-ec] FW: [sv-ac] Hierarchical reference in clocking signal

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Surya Pratik Saha
Sent: Wednesday, July 11, 2007 2:23 PM
To: sv-bc@eda-stds.org; sv-ac@eda-stds.org
Subject: [sv-ac] Hierarchical reference in clocking signal


Hi,
As per clocking domain syntax, the signal identifier is a simple
identifier, not hierarchical identifier. This is the snippet of BNF:

clocking_declaration ::=
.............
list_of_clocking_decl_assign ::= clocking_decl_assign { ,
clocking_decl_assign }
clocking_decl_assign ::= signal_identifier [ = expression ]
signal_identifier ::= identifier


But there is an e.g. in the LRM using hierarchical reference as signal
identifier (page no. 218).
clocking cd1 @(posedge a.clk); 
input a.data; 
output a.write; 
inout state = top.cpu.state; 
endclocking

Which is wrong as per BNF. So is the e.g. valid, or just to used for
understanding. No standard simulators passing this case.

-- 
Regards
Surya

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