RE: [sv-ec] FW: Vectors used in concatenation with string

I would say that it is illegal.

 

You can only concatenate a data object of type string with other data
objects of type string and with string literals.

 

In order to combine an integral type with a string type, you would have
to explicitly cast the integral type to a string type.

 

Shalom

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Mehdi Mohtashemi
Sent: Tuesday, July 10, 2007 7:05 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] FW: Vectors used in concatenation with string

 

FWD, non-subscriber question to the reflector.

 

________________________________

From: wojtekf [mailto:wojtek.filip@aldec.com] 
Sent: Tuesday, July 10, 2007 5:53 AM
To: owner-sv-ec@eda.org
Cc: 'Daniel Mlynek'
Subject: Vectors used in concatenation with string

Hello!

 

How should we treat string concatenation with integral types (e.g.
vector of  bit) ?  Is it legal at all ?  

I'm not sure about that after reading LRM. 

 

Let's say we have code :

 

...

bit [11:0] b1 = 12'b011001010010;
reg [6:0] r1 = 7'b0010100;

string str1,str2;

...

 

str1={str2,b1,r1};    


...

 

If above is legal what should be result?

a) b1 and r1 should be concatenated into one bit-stream and than
expanded to width equal 24 bits ( eight multiple)

 

b) b1 should be expanded to 16 bits, separately r1 should be expanded to
8 bits separately , than whole bit-stream would be assigned to str1.

 

c) something else??

 

 

Best regards,

Wojciech Filip


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