Dave, > We already have sampled value functions that are persistent until the > end of the time slot. We just need to define them for use when the > signal it the sampling clock itself. That's not hard to do. $rose(clk) > would be true when clk is 0 in the preponed region and goes to 1 any > time in the current time slot. Yes... I've already (publicly!) given up on 1715 and suggested that it be withdrawn, or whatever the right mechanism is. I was trying here to address what seemed to me to be a completely tangential discussion that somehow got itself hooked to the consideration of cb.triggered. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sat May 5 01:21:24 2007
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