RE: [sv-ec] Fwd: Cliff's Votes - E-mail Vote (part 2) Closes 12am PST May 2 2007

Brad,

You are right, and I am wrong.  So much for my two cents worth--I guess I
forgot to adjust for inflation :(

I'm so used to modeling for with this restriction of specifying an edge on
all signals in the sensitivity list in mind, that I assumed the LRM
specified it for always_ff, as well.  I did some digging to satisfy my own
curiosity, and found that this requirement was discussed in some early
"Verilog++" committee meetings, but never made it into any version of a SV
LRM.  Not even my old SUPERLOG manual requires it, though I think I recall
that the Co-Design SUPERLOG simulator imposed the restriction (and hence the
early committee discussions on it).  

This means Cliff and Don's example is legal syntax when using always_ff (at
least the sensitivity list part).  I'll have to play around with the example
someday and see if the tools I use allow it.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
 

> -----Original Message-----
> From: owner-sv-ec@server.eda.org 
> [mailto:owner-sv-ec@server.eda.org] On Behalf Of Brad Pierce
> Sent: Friday, May 04, 2007 12:11 PM
> To: sv-ec@server.eda.org
> Subject: RE: [sv-ec] Fwd: Cliff's Votes - E-mail Vote (part 
> 2) Closes 12am PST May 2 2007
> 
> >Currently, always_ff requires that either negedge or posedge be
> specified
> >for each signal in the sensitivity list.
> 
> No, it doesn't.  The additional restrictions imposed by 
> synthesis tools
> are irrelevant to what the LRM requires.  Again, see
> 
>      http://www.eda-stds.org/sv-ac/hm/3510.html
> 
> -- Brad
> 
> 
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