RE: [sv-ec] Fwd: Cliff's Votes - E-mail Vote (part 2) Closes 12am PST May 2 2007

Currently, always_ff requires that either negedge or posedge be specified
for each signal in the sensitivity list.  This is a synthesis restriction
imposed by one synthesis vendor, but not any others that I know of.  The
"fix" Cliff and Don have suggested, and which I agree with, would require
relaxing that rule so that reset and set can trigger on either edge.
Relaxing the rule would also allow using both edges of clock for
double-data-rate devices, as well.  Relaxing the rule would be backward
compatible with current behavior.  I would support a proposal to either
relax the sensitivity list rules of always_ff, or add an "always_ddr" or
similar construct that had the relaxed sensitivity list requirements, but
kept the other synthesis benefits of always_ff.

My two cents worth.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
 

> -----Original Message-----
> From: owner-sv-ec@server.eda.org 
> [mailto:owner-sv-ec@server.eda.org] On Behalf Of Brad Pierce
> Sent: Friday, May 04, 2007 10:35 AM
> To: sv-ec@server.eda.org
> Subject: RE: [sv-ec] Fwd: Cliff's Votes - E-mail Vote (part 
> 2) Closes 12am PST May 2 2007
> 
> Don writes --
>  
> > I am not sure that always_ff is right (best) for this model
> > since only one of the items in the sensitivity list has a
> > posedge/negedge on it.
>  
> Why would that be a problem for always_ff?  See
> 
>   http://www.eda-stds.org/sv-ac/hm/3510.html
> 
> -- Brad
> 
> 
> -- 
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