RE: [sv-ec]E-mail Vote on mantis item 890: Closes 12am PST April 6th

Hi, Doug -

Thanks for the updates and clarifications. This certainly makes 
synchronous drives easier to explain.

I think there is still one more friendly amendment in the example I 
noted earlier - page 5 of the proposal

logic a, b, c;
clocking cb @(posedge clk);
   inout a;
   output b;
endclocking

initial begin
   cb.a <= c;    // The value of a will change in the Re-NBA region
   cb.b <= cb.a; // b is assigned the value of a before the change
end

I believe you at least want:
wire  a;
logic b, c;

An inout has two driving sources, the port and the synchronous drive 
and inouts have always required a resolved net-type on the port 
declaration for either programs or modules. Logic types will give a 
compilation error if two driving sources are detected.

I vote yes with or without the friendly amendment. We can always fix 
it later and the update is by far better than the current 
documentation. Good work, Doug!

Regards - Cliff

At 11:47 AM 4/4/2007, Warmke, Doug wrote:
>Hi Cliff,
>
>Thanks for the friendly amendments.
>I took care of all of them except as follows.
>
>There is a misunderstanding in your comments inre Re-NBA.
>ALL synchronous drives schedule into the Re-NBA region,
>after our last face-to-face.  It used to be that synchronous
>drives running in design threads were scheduled in NBA, and
>synchronous drives running in program threads scheduled in
>the Re-NBA region.  But at the face-to-face we decided that
>all synchronous drives are to be scheduled in Re-NBA.
>
>The amended proposal has been uploaded to Mantis.
>(http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000890)
>
>Regards,
>Doug

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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