Re: [sv-ec] Mantis 890 Question - ##1 at time-0??

Hi Cliff,

I don't think your question is specific to time 0. Instead, it is a question
about the reliability of using ## cycle delays within code that executes
in the Active region set.

The problem is that the clocking event specified in the default clocking block
will usually occur during the processing of the Active region set. If a
process which gets updated within the Active region set executes a ## delay in
the same time slot that the clocking event occurs in, there is a potential race
condition.

Note that this potential race condition does not occur for ## cycle
delays used in concurrent assertions or in program blocks since both of those
constructs are not executed within the Active region set.
Immediate assertions seem to also suffer from this race condition.

This appears to be yet another situation where a race condition can occur.
The text of proposal for 890 may need to be clarified in this regard.

Neil



Clifford E. Cummings wrote On 03/17/07 18:50,:
> Hi, All -
> 
> Try the attached test and see if it makes sense. The code is also shown below.
> 
> The key piece of code and the part I question is the init_task, which 
> is called at time-0:
> 
>    task init_reset;
>      `ifdef NODLY
>          rst_n <= '0; // +define+NODLY
>      `else
>      ##1 rst_n <= '0; // Should this happen at time-0 or time-10?
>      `endif
>      ##1 rst_n  = '1;
>    endtask
> 
> If you run the simulation with +define+NODLY, the two implementations 
> that I am currently running both execute the these statements at 
> time-0 (the ##1 sees the negedge clk at time 0).
> 
>    task init_reset;
>          rst_n <= '0; // Should this happen at time-0 or time-10?
>      ##1 rst_n  = '1;
>    endtask
> 
> Have we defined the ##1 to wait until the next negedge clk if a 
> negedge clk has happened coincident with the ##1?
> In the future, will the ##1 wait until the first negedge clk not at time 0?
> 
> 
> If you run the simulation WITHOUT +define+NODLY, the two 
> implementations that I am currently running both execute the first 
> statement at time-0 and the second statement at time10 (the first ##1 
> sees the negedge clk at time 0).
> 
>    task init_reset;
>      ##1 rst_n <= '0; // Should this happen at time-0 or time-10?
>      ##1 rst_n  = '1;
>    endtask
> 
> In the future, will the first ##1 wait until the first negedge clk 
> not at time 0?
> 
> I was expecting the first ##1 to wait a full cycle. Is the intent of 
> Mantis 890?
> 
> I can live with either interpretation but I want to make sure there 
> is agreement on the interpretation.
> 
> Regards - Cliff
> 
> Full example:
> 
> 
> `define CYCLE 10
> `timescale 1ns / 1ns
> module clk0test;
>    logic clk, rst_n;
> 
>    //-------------------------------------------------------------------
>    // Clock oscillator
>    //-------------------------------------------------------------------
>    initial begin
>      clk <= 0;
>      forever #(`CYCLE/2) clk = ~clk;
>    end
> 
>    //-------------------------------------------------------------------
>    // First negedge clk at time 0
>    //-------------------------------------------------------------------
>    default clocking cb0 @(negedge clk);
>    endclocking
> 
>    //-------------------------------------------------------------------
>    // Test code
>    //-------------------------------------------------------------------
>    initial begin
>      init_reset;
>      ##6;
>      reset;
>      ##4;
>      reset(3);
>      ##3 $finish;
>    end
> 
>    //-------------------------------------------------------------------
>    // Reset commands: init_reset (time-0 reset) & reset
>    //-------------------------------------------------------------------
>    task init_reset;
>      `ifdef NODLY
>          rst_n <= '0; // +define+NODLY
>      `else
>      ##1 rst_n <= '0; // Should this happen at time-0 or time-10?
>      `endif
>      ##1 rst_n  = '1;
>    endtask
> 
>    task reset (input int cnt=1);
>      ##1 rst_n  = '0;
>      repeat(cnt) ##1;
>          rst_n  = '1;
>    endtask
> 
>    initial begin
>      $timeformat(-9,0,"ns",6);
>      $monitor("%t: rst_n=%b", $time, rst_n);
>    end
> endmodule
> 
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
> 

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Neil Korpusik                                     Tel: 408-720-4852
Senior Staff Engineer                             Fax: 408-720-4850
Frontend Technologies - ASICs & Processors (FTAP)
Sun Microsystems
email: neil.korpusik@sun.com
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