[sv-ec] SystemVerilog Interoperability survey

<forwarding email from Logie Ramachandran>

-------- Original Message --------
Subject: [sv-bc] SystemVerilog Interoperability survey
Date: Wed, 28 Feb 2007 11:21:30 -0800
From: Logie Ramachandran <Logie.Ramachandran@synopsys.com>
To: sv-xc@eda.org, sv-bc@eda.org, sv-ac@eda.org, sv-ec@eda.org, sv-cc@eda.org, ieee1800@eda.org


The SV-XC committee is soliciting your inputs on SystemVerilog
Interoperability with VHDL, AMS and SystemC. The committee has
prepared a survey in order to gather user requirements and help
focus the standardization activities based on your requirements.

The survey is available at
http://www.eda-stds.org/sv-xc/otherdocs/survey1.0.txt

This is a simple text file. You can save it on your desktop
and fill it out with your normal editor.

The instructions are provided in the survey. Please send your
feedback to the committee by emailing to sv-xc@eda.org. If you
like you can also send your completed survey to logie@synopsys.com
or somdipta@ti.com

We would appreciate your response by 3/15/2007.


Somdipta Roy (TI)
Logie Ramachandran (Synopsys)




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