I don't recall this being raised in EC, and it might be of interest. SV-AC has a proposal for putting assertions (as opposed to properties) in a clocking block. http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001547 See also these email threads: http://www.eda-stds.org/sv-ac/hm/2542.html http://www.eda-stds.org/sv-ac/hm/3323.html -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 21 07:00:51 2007
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