[sv-ec] SV-890-6.pdf is ready

Hi SV-EC,

I decided to go ahead and incorporate Jonathan's detailed and valuable
comments into the 890 proposal.  Now, SV-890-6.pdf is available in the
attachments section of
    http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000890

Only one of Jonathan's comments is still unaddressed.  Namely the
wording of the paragraphs discussing the lhs vs. rhs intra-assignment
usage of the cycle_delay (##) operator.  We'll continue to hash that
out and hopefully get it resolved in 890-7.

Please take a look.

Regards,
Doug

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