Hi All, At last the next draft of SV-890 is ready. Please look at the last attachment in the list at http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000890 All comments are welcome. I'm sure there is wording that can be improved, though I think I've done justice to all the meeting minutes and emails related to 890 since the face-to-face in November. Just as a reminder, I consdider that 890 addresses the issues in the following Mantis items, which are still open: http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000236 http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000551 http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000564 http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000608 http://www.verilog.org/svdb/bug_view_page.php?bug_id=0000609 Also, we still haven't ironed out exactly what to do about the clocking of the cycle_delay in cb.v <= ##N e; We can talk about that on email and in the next meeting. Best regards, Doug -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Feb 5 16:42:38 2007
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