<forwarding bounced email from Greg Jaxon> -------- Original Message -------- Subject: Re: [sv-bc] Enum used in concat or assignment pattern Date: Tue, 02 Jan 2007 11:21:40 -0600 From: Greg Jaxon <Greg.Jaxon@synopsys.com> To: Moumita Das <moumita@cal.interrasystems.com> CC: sv-ec <sv-ec@eda-stds.org>, sv-bc <sv-bc@eda-stds.org> Since it infers the assignment out3=x.b2, it should be just as erroneous as out3=out4; both assign a byte to a strict SV enum. Moumita Das wrote: > Hello, > > According to IEEE std 1800-2005 IEEE standard for System Verilog sec > 4.10.3- > > "SystemVerilog enumerated types are strongly typed; thus, a variable of > type enum cannot be directly assigned a value that lies outside the > enumeration set unless an explicit cast is used or unless the enum > vari-able is a member of a union. This is a powerful type-checking aid > that prevents users from accidentally assigning nonexistent values to > variables of an enumerated type. The enumeration values can still be > used as constants in expressions, and the results can be assigned to any > variable of a compatible integral type." > > So for the following testcase assignment out3=out4 is an invalid statement. > So my query is 2nd assignment that is '{out4, out3} =x is valid or not? > > testcase: > ------ > > typedef enum logic [7:0] {e0, e1} u_t1; > typedef struct {byte b1; byte b2;} u_t2; > > module var7(input u_t1 in1, input byte in2); > wire [8:0] myvar ; > u_t1 out3; > byte out4; > u_t2 x; > initial > begin > out3 = out4; // This is an error case > '{out4, out3} =x ; //This case is valid or not? > end > endmodule > > regards, > > Moumita > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jan 3 16:20:40 2007
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