[sv-ec] Issues in Pattern Matching

Hi,

In SV LRM 1800-2005 IEEE Standarad for System Verilog we found a rule-

conditional_statement ::= if ( cond_predicate ) statement_or_null [ else 
statement_or_null ]

cond_predicate ::= expression_or_cond_pattern { &&& 
expression_or_cond_pattern }

expression_or_cond_pattern ::= expression | cond_pattern

cond_pattern ::= expression matches pattern

So as per BNF  we can use "&&&" operator in condition of if statement 
but LRM
does not restrict the usage.

And the same thing is also true for conditional expression-

conditional_expression ::= cond_predicate ? { attribute_instance } 
expression : expression


but for case statment this "&&&" is used only for pattern matching where
1st expresssion must be a pattern and only one expression can be used 
after "&&&".

So my question is following testcases are vaild or not -

1) if(a!=0 &&& b!=0)
2) assign y = a > b &&& b > c  ? c : d

If there are valid cases then what will be the semantic difference 
between "&&" and "&&&".


Also LRM is not clear on the associativity of "matches" and "&&&".
So following case
assign y = a > b matches b ? c : d

will be resolved as:
assign y = (a > b) matches b ? c : d
or
assign y = a > ( b matches b? c : d)

Thanks,
Moumita