RE: [sv-ec] Program Block / Reactive Region Use Cases & Requirements

From: Steven Sharp <sharp_at_.....>
Date: Fri Dec 08 2006 - 15:13:07 PST
All of Rob Slater's points in his recent email match my own opinions
about the historical reasons for the scheduling regions, and whether
they should be needed in SystemVerilog.

I have hesitated to argue this too strongly, since I thought there
might be a user viewpoint that I was not understanding.  But I am
certainly willing to support these arguments when they come from an
experienced user.

Steven Sharp
sharp@cadence.com
Received on Fri Dec 8 15:13:12 2006

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