[sv-ec] program questions

I do not know if there were any other responses than Cliff's to the
email I sent on Monday.
It appears that the cadence email addresses do not got through.
 
Anyways this email is an answer to Cliff's response since this is the
only one I received...
 
From Cliff's response, it looks like the concept of a program variable
can go away completely since
a variable will get the assignment semantics from the region the
assignment was made. 
If a variable is assigned in an initial block of a program, it gets
assigned in the reactive region 
(potentially the re-nba region if that was a non blocking assignment).
 
It also seems to me that the restrictions we initially had on programs
are going away (no NBA to variables
declared in programs, no continuous assignments) except for the fact
that programs are not allowed to have 
sub instances and always blocks.
 
The only remaining question is what exactly happens when a program
contains a continuous assignemnt to a
wire declared in the DUT. 
1. Does the wire effective value (resolution of the drivers) happens
immediately and
is immediately visible a #0 later in the program block? 
2. When is any fanout of the wire triggered?
if there is a @(w) in the DUT, does the process wakes up once the whole
reactive cycle is finished?
 
Is the sequence of actions:
     1. the simulator executes the continous assignment  and updates the
driver of the wire in the program,
     2. resolution of the wire effective value 
     3. #0 new wire value is now visible in the program
     4. continue executing the little loop in the reactive region until
done 
     5. execute the big design cycle and wake up the fanout of the wire
 
 
Why are we calling this the big loop and the small loop? It looks to me
that the design loop and the reactive loop now
are symmetric.
 
Francoise
       '