[sv-ec] programs discussion and resulting questions

We had a discussion internally at Cadence about the proposed changes to
program blocks.
That discussion generated a few questions which are listed below and
which we would like to
see answers:
 

With the new proposed scheme where tasks and functions called from the
program block

get reactive scheduling semantics whereas if they are called from a
design process, they get regular

scheduling semantics:

1. NBAs: 

  1.1 Are NBAs to design variables inside a task being called by the
program be scheduled in the Reactive NBA region or

    the design NBA region

 

  1.2 What is the behaviour of a NBA to a concatenation of a module
variable and program variable on the target of the NBA?

       {mv, pv} <= 2'b00;

 

 2. Called from a foreign language:

What are the scheduling semantics for a SV task called from another
language (VHDL, systemC, C, DPI)?

 

 

 3.  Program constructs restrictions

    3.1 Since the proposal is that design tasks called from the
testbench get reactive scheduling, are such tasks going to 

          be limited to language constructs allowed in programs? For
example blocking assignments are not allowed in programs, are

          we going to have to dynamically check for blocking assignments
if the task is called from a program based process?

    3.2 Are task functions local variables considered to be program or
design variables? Do blocking assignment program

          restrictions apply to tf local variables? 

    3.3 A task or function can access a static variable defined outside
the task or function, are blocking assignment to out of tf

          static variables allowed when the tf is called from the
program?

 

 4. Spawned processes

    What are the scheduling semantics of fork join processes of a design
task or function when the task/function is called

     from a program?

 

5. Class variables

    5.1 Are class variables considered design or program variables?

     5.2 Are class properties considered design or program variables? If
we were going to allow NBAs to class properties,

          where would these NBAs be scheduled? (There has been some user
request to remove the current limitation of no NBAs to

         class properties so we need to have an answer for the future).

 

6. Continuous assignments

 Is it legal to have continuous assignments to wires in a program?

7. Program inout ports

   7.1 Can a program have inout ports (wires)? There is an example in
the LRM of a program with an inout wire port.

   7.2 How does the program drive the wire?