Date: Mon Nov 20 2006 - 04:23:02 PST
True and I agree. But 1800 confuses the issue by writing in 3.6, "A string literal is enclosed in quotes and has its own data type." I think the combination of 3.6 and 6.3.2 is confusing. The fact is that the Verilog-AMS committee was misled by this. Shalom ________________________________ From: Feldman, Yulik Sent: Sunday, November 19, 2006 3:49 PM To: Bresticker, Shalom; sv-ec@server.eda-stds.org Subject: RE: [sv-ec] assigning string literal to parameter 1364 3.6 "Strings" says: "Strings used as operands in expressions and assignments shall be treated as unsigned integer constants represented by a sequence of 8-bit ASCII values, with one 8-bit ASCII value representing one character." I would treat an "unsigned integer" as an integral type, making an "assignment" of a string literal to parameter without an explicit type declaration legal. --Yulik. ________________________________ From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Sunday, November 19, 2006 3:35 PM To: sv-ec@server.eda-stds.org Cc: Bresticker, Shalom Subject: [sv-ec] assigning string literal to parameter 6.3.2 ("Value parameters") says, "In an assignment to, or override of, a parameter without an explicit type declaration, the type of the right-hand expression shall be real or integral." This has been interpreted by some as excluding string literals. I don't think that was the intent and it would not be back-compatible. Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
