[sv-ec] List of port expressions

<forwarding email from Daniel M.>


-------- Original Message --------
Subject: List of port expressions
Date: Thu, 09 Nov 2006 10:56:21 +0100
From: danielm <danielm@aldec.com.pl>
To: owner-sv-ec@eda.org

SV defines list of port expressions (19.9). This is defined only for ANSI
style headers. This is mistake in syntax production?

port ::=
[ port expression ]
| . port identifier ( [ port_expression ] )

ansi_port_declaration ::=
[ net_port_header | interface_port_header ] port_identifier {
unpacked_dimension }
| [ variable_port_header ] port_identifier { variable_dimension } [ =
constant_expression ]
| [ net_port_header | variable_port_header ] . port_identifier ( [
expression ] )


Diference in ANSI_port and port definition which I dont understand is:
-for ANSI: port_identifier ( [ expression ]
- for nonANSI :. port_identifier ( [ port_expression ] )

Port expression is limited only to port reference.
So according to LRM I cannot have in non ANSI style:
module(.a(sig[0])); /*
  input a;
  wire [1:0] sig;
endmodule

But in ANSI style i can have:
module(input .a(sig[0]));/**
  wire [1:0] sig;
endmodule

Question is : is really (*) forbidden?

DANiel