RE: [sv-ec] Auto bin generation when user defined bins are defined on crosses

From: Warmke, Doug <doug_warmke_at_.....>
Date: Wed Nov 08 2006 - 17:41:24 PST
A Mantis item has been entered for this issue at
   http://www.verilog.org/svdb/bug_view_page.php?bug_id=0001671

Comments welcome.
No proposal available yet, as discussion and consensus is needed first.

Regards,
Doug 

> <Forwarding email from  Satya Ayyagari>
> 
> -------- Original Message --------
> Subject: Auto bin generation when user defined bins are 
> defined on crosses
> Date: Wed, 08 Nov 2006 15:00:16 -0800
> From: Ayyagari, Prabhakar S <prabhakar.s.ayyagari@intel.com>
> To: owner-sv-ec@eda.org
> CC: Ayyagari, Prabhakar S <prabhakar.s.ayyagari@intel.com>
> 
> Hi:
> 
> I have a couple of questions on auto generated bins when user defined
> bins are defined.
> 1. When a coverpoint has user defined bins should the tool 
> also generate
> auto bins?
> 2. When cross coverage has user defined bins should the tool also
> generate auto bins for the remaining product space excluding 
> illegal and
> ignore?
> 
> Varied interpretations can be made based on sections 18.4.2, 
> 18.5.1 and
> 18.10.2.
> 18.4.2 - "Users can either let the tool automatically create 
> state bins
> or explicitly define named bins for each coverage point."  For a
> coverpoint it seems to be an either/or thing.
> 18.5.1 makes no mention of auto generated bins for crosses and 18.10.2
> using a term Bc for auto generated bins which gets added with user
> defined bins for cross coverage computation.
> 
> Thanks,
> Satya Ayyagari
> 
> 
Received on Wed Nov 8 17:41:27 2006

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