RE: [sv-ec] Review of Mantis 890 (clocking blocks)

Doesn't Verilog usually refer to a time queue to mean a time slot?
 
 


________________________________

	From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf
Of Bresticker, Shalom
	Sent: Tuesday, September 26, 2006 8:36 AM
	To: Arturo Salz; sv-ec@eda.org
	Subject: RE: [sv-ec] Review of Mantis 890 (clocking blocks)
	
	

	"time step" is uses throughout the LRM with a different meaning,
similar to what you call "time slot".

	 

	Shalom

	 

	To avoid further confusion, I believe the following taxonomy
will be useful:

	*      time slot - A time for which there are events to process
- The scheduled events at a specific time define a time slot

	*      time step - The time between time slots: The step that
takes the simulator from one slot to the next

	*      time unit - The physical units (s, ms, us, ns, ps, fs)
associated with a time literal plus the unit step