[sv-ec] Current 15.10 Discussion

NEW Modified PROPOSAL:
The cycle delay statement shall wait for the specified number of 
clocking events. If a ##1 statement is executed at a simulation time 
that is not coincident with the associated clocking event, the 
calling process shall be delayed a fraction of the associated clock cycle.

Assuming the following declaration:
default clocking @(posedge clk);

These semantics guarantee that for N>0 the following two statements 
are equivalent:
## N;
repeat N @(posedge clk);

For N=0, if the event was triggered, do nothing, otherwise the ##0 
behaves like ##1. This is similar to wait on event.triggered.


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