RE: [sv-ec] Access to interface objects via virtual interface

Sorry, I had Vera's virtual ports and dynamic port binds mixed up. I
don't claim to be a Vera expert.

 

I also have to admit to forgetting upload the actual proposal, which I
intended to do before sending the e-mail. I think you'll see that I'm
just modifying section 20.9 on access rights to include virtual
interfaces.

 

See http://www.eda-stds.org/svdb/file_download.php?file_id=1588&type=bug

 

Dave

 

 

________________________________

From: Arturo Salz [mailto:Arturo.Salz@synopsys.com] 
Sent: Saturday, September 02, 2006 1:32 AM
To: Rich, Dave; sv-ec@eda.org
Subject: RE: [sv-ec] Access to interface objects via virtual interface

 

Dave,

 

First, a minor clarification: Virtual interfaces were added in response
to a specific request from SUN, as documented in the SV-EC July 21, 2003
minutes:

 

    EXT-3:
        Neil - described the use of virtual ports within Vera and that
            something lack this is required within SystemVerilog.

 

Hence, virtual interfaces were motivated by the virtual-ports feature of
Vera, but they were designed specifically for SytemVerilog. They did not
"come" from Vera, nor do they have anything to do with Vera's dynamic
port bind feature, which is a different construct altogether.

 

As for your request, I fail to see how someone would surmise that it is
illegal to reference tasks and functions through a virtual interface. Of
course they are. That's what the statement "all the components of the
underlying interface instance are directly available to the virtual
interface". I have no objection to clarifying this, but I wonder how
your verbiage "every identifier inside an interface" is any clearer from
"all components"? In fact, your statement is not true since types
defined in an interface are not available through a virtual interface.
BTW, according to Webster's, component means "a constituent part", and
tasks/functions defined within the interface are definitely a
constituent part of that interface.

 

            Arturo               

 

________________________________

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Rich, Dave
Sent: Friday, September 01, 2006 2:34 PM
To: sv-ec@eda.org
Subject: [sv-ec] Access to interface objects via virtual interface

 

Currently, the LRM (20.8)  says this about what's legal to reference via
a virtual interface handle:

 

"Once a virtual interface has been initialized, all the components of
the underlying interface instance are directly available to the virtual
interface via the dot notation."

 

There is no definition of what a "component" is could be.

 

The virtual interface feature in SystemVerilog comes from the dynamic
port bind feature of Vera which did not have the concept of defining
tasks or functions as part of its port declaration. In the transition to
SystemVerilog interfaces, given the fact that they do allow tasks and
function declarations, it seems like a natural feature to be able to
call them. The LRM just needs to spell out exactly what is legal to
access via a virtual interface handle.

 

I think that every identifier inside an interface is legal to access via
a virtual interface, assuming it's legal to do so with a static
hierarchal path to the interface.

 

This is mantis 1580

 

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625