[sv-ec] Access to interface objects via virtual interface

Currently, the LRM (20.8)  says this about what's legal to reference via
a virtual interface handle:

 

"Once a virtual interface has been initialized, all the components of
the underlying interface instance are directly available to the virtual
interface via the dot notation."

 

There is no definition of what a "component" is could be.

 

The virtual interface feature in SystemVerilog comes from the dynamic
port bind feature of Vera which did not have the concept of defining
tasks or functions as part of its port declaration. In the transition to
SystemVerilog interfaces, given the fact that they do allow tasks and
function declarations, it seems like a natural feature to be able to
call them. The LRM just needs to spell out exactly what is legal to
access via a virtual interface handle.

 

I think that every identifier inside an interface is legal to access via
a virtual interface, assuming it's legal to do so with a static
hierarchal path to the interface.

 

This is mantis 1580

 

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625