RE: [sv-ec] constraint_mode is a task?

Mike,

I believe the intent was to be the declaration or prototype of the
built-in function.

The issue of task or function is legacy from Vera. Vera did not care
about the difference between tasks and functions, and unless a task has
the potential to block, it should be declared as a void function in
SystemVerilog. There are many occurrences of this in the LRM and a
number of proposals to fix this already resolved.

This syntax is a special case to handle the lack of support for variable
numbers of arguments (varargs) in SystemVerilog. I believe this is a
frequently requested enhancement and would get rid of this special case.

Dave




> -----Original Message-----
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org]
On
> Behalf Of Michael Burns
> Sent: Tuesday, August 22, 2006 2:32 PM
> To: sv-ec@server.eda.org
> Subject: [sv-ec] constraint_mode is a task?
> 
> 
> Hi folks,
> 
> Section 13.8 defines constraint_mode on a constraint like this:
> 
> The syntax for the constraint_mode() method is as follows:
>    task object[.constraint_identifier]::constraint_mode( bit on_off );
> or
>    function int object.constraint_identifier::constraint_mode();
> 
> Is this intended to be a declaration of the built-in constraint_mode
> method or the calling of it? It looks like it's trying to be both. The
> declaration would look like this:
> 
>    task constraint_mode( bit on_off );
> or
>    function int constraint_mode();
> 
> and the calling like this:
> 
>    object[.constraint_identifier].constraint_mode( bit on_off );
> or
>    int foo = object.constraint_identifier.constraint_mode();
> 
> Am I making sense?
> 
> Also, the task version would be much better defined as a void function
> so it could be called from within other tasks.
> 
> Thanks,
> Mike Burns
> Freescale