RE: [sv-ec] SV: class instance inside an interface

Ben,

There are orthogonal restrictions on the *context* of the reference to a dynamically created object: procedural or non-procedural. (Section 6.6). It has nothing to do with module/program/interface, etc.

The initial block is a procedural context. The concurrent assertion is a non-procedural context.

Dave


> -----Original Message-----
> From: vhdlcohen@aol.com [mailto:vhdlcohen@aol.com]
> Sent: Monday, July 10, 2006 9:28 AM
> To: Rich, Dave; sv-ec@server.eda.org
> Subject: Re: [sv-ec] SV: class instance inside an interface
> 
> 
> Dave,
> Here is code that fals to compile when the class instance is used in an
> assertion.
> It seems OK in the assignment though.  ???
> 
> class configuration;
>   bit addr = 1;
> endclass:configuration
> 
> interface itf (input logic Clk, input logic Rst);
>   logic [7:0] A ;
>   logic [2:0] B ;
> 
>   configuration cfg_local=new;
>   initial A[0]Ïg_local.addr;  // Compiles OK HERE
>   // some checker:
>   property signal_valid (A, clk, B, addr);
>     @(posedge clk)
>     if(addr)
>     |A |-> !$isunknown(B);
>   endproperty
> 
>   assert_signal_valid:
>      assert property (signal_valid(A, Clk, B, cfg_local.addr)) // here
> is the compile error
>     else $display($time, " signal_valid failed.");
> endinterface: itf
> 
> 
> ** Error: test.sv(19): (vlog-2110) Illegal reference to class
> "cfg_local".
> 
> 
> -----Original Message-----
> From: Rich, Dave <Dave_Rich@mentor.com>
> To: vhdlcohen@aol.com; sv-ec@server.eda.org
> Sent: Mon, 10 Jul 2006 09:02:06 -0700
> Subject: RE: [sv-ec] SV: class instance inside an interface
> 
>   A class is a kind of data type (section 4.12), and you can declare a
> class anywhere it is valid to declare data type. I don't think there is
> any ambiguity.
> 
> Dave
> 
> 
> > -----Original Message-----
> > From: owner-sv-ec@server.eda-stds.org [mailto:owner-sv-ec@server.eda-
> > stds.org] On Behalf Of vhdlcohen@aol.com
> > Sent: Monday, July 10, 2006 8:22 AM
> > To: sv-ec@server.eda.org
> > Subject: [sv-ec] SV: class instance inside an interface
> >
> >  From Adrian Coman,
> >
> http://verificationguild.com/modules.php?name=Forums&file=viewtopic&pT6
> > 1#5461
> > The SV LRM doesn't say anything about classes inside interfaces, only:
> > Quote:
> > Page 349, IEEE Std 1800(tm)-2005: An interface can have parameters,
> > constants, variables, functions, and tasks.
> >
> > So it doesn't specifically forbidden the usage of classes inside
> > interfaces.
> > _________________
> >
> > I agree with you that the LRM is ambiguous. I did a quick test on a
> > simulator, and it compiled OK.
> > Translation: As of right now, it's a matter of interpretation. But
> > logically, in some respects interfaces are similar to modules in that
> > they can have arguments, tasks, and temporal properties, among other
> > things. Thus, since modules can have class intances, why should the
> > interfaces be excluded. It seems that this is the path that vendors
> are
> > taking.
> > Ben Cohen
> >
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> 
> 
> 
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