RE: [sv-ec] SV: class instance inside an interface

From: Rich, Dave <Dave_Rich_at_.....>
Date: Mon Jul 10 2006 - 09:02:06 PDT
A class is a kind of data type (section 4.12), and you can declare a
class anywhere it is valid to declare data type. I don't think there is
any ambiguity.

Dave


> -----Original Message-----
> From: owner-sv-ec@server.eda-stds.org [mailto:owner-sv-ec@server.eda-
> stds.org] On Behalf Of vhdlcohen@aol.com
> Sent: Monday, July 10, 2006 8:22 AM
> To: sv-ec@server.eda.org
> Subject: [sv-ec] SV: class instance inside an interface
> 
>  From Adrian Coman,
>
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&pT6
> 1#5461
> The SV LRM doesn't say anything about classes inside interfaces, only:
> Quote:
> Page 349, IEEE Std 1800(tm)-2005: An interface can have parameters,
> constants, variables, functions, and tasks.
> 
> So it doesn't specifically forbidden the usage of classes inside
> interfaces.
> _________________
> 
> I agree with you that the LRM is ambiguous. I did a quick test on a
> simulator, and it compiled OK.
> Translation: As of right now, it's a matter of interpretation. But
> logically, in some respects interfaces are similar to modules in that
> they can have arguments, tasks, and temporal properties, among other
> things. Thus, since modules can have class intances, why should the
> interfaces be excluded. It seems that this is the path that vendors
are
> taking.
> Ben Cohen
>
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Received on Mon Jul 10 09:02:10 2006

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