RE: [sv-ec] Query regarding illegal bins

From: Rich, Dave <Dave_Rich_at_.....>
Date: Tue Jun 20 2006 - 23:14:15 PDT
Abhishek,

The bin guard expression only serves to prevent incrementing the bin
counter, it does not change bin structure. Since ignore_bins and
illegal_bins aren't part of the coverage calculation, the guard has no
effect on the final coverage. You may want to look at
http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001237.

Dave


> -----Original Message-----
> From: owner-sv-ec@server.eda-stds.org [mailto:owner-sv-ec@server.eda-
> stds.org] On Behalf Of Abhishek Tiwari
> Sent: Tuesday, June 20, 2006 8:41 AM
> To: sv-ec@server.verilog.org
> Subject: [sv-ec] Query regarding illegal bins
> 
> Hi
> 
> I have a query regarding 'iff' with illegal bins .
> 
> Consider the following example:
> 
> coverpoint a {
>   bins b1[] = {0, 1, 2, 3};
>   illegal_bins il_bins = {0} iff x+y;  // Note guard expression
> }
> 
> Now, as per LRM, bins are effective only when guard expression
> evaluates to true. I believe this will apply for
> illegal_bins/ignore_bins. If
> that is the case, values 0 will only be ignored iff "x+y"
> is true while sampling. Now, it may happen that value 0 is ignored
> during one sampling event (x+y true) and not ignored (x+y false)
> during another sampling event.
> 
> In such scenario, LRM does not specify how to calculate the final
> coverage.
> 
> Thanks
> Abhishek
Received on Tue Jun 20 23:14:22 2006

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