Re: [sv-ec] Proposal uploaded for 1313 (coverpoint and bins expression resolution)

Gordon Vreugdenhil wrote:

> 
> 
> Swapnajit Chakraborti wrote:
> 
>> Hi Gord,
>>
>> In general, does Verilog/SysV LRM states anywhere
>> that there should be a warning if the rhs of a
>> variable assignment is out of range of lhs?
> 
> 
> No - Verilog automatically truncates.
> 
> The reason for the special behavior here (and why it might be
> reasonable to specify values rather than leave it be "implementation
> defined behavior), is that for coverpoint bins ranges you are
> really describing a range in values in a "wider" domain that either
> the coverpoint expression or the bins expression.  This came up
> in the original email thread; you might want to look at some of
> the examples in the email thread starting at:
>    http://www.eda.org/sv-ec/hm/2819.html
> 
> A simple example is the issue is that for a bins range of 0..8
> related to a coverpoint expression of 3 bits, you really do not want
> this to silently become a range of 0..1.
                                      ^^^^
<blush> Should be "0..0" of course.

Gord.


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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com