RE: [sv-ec] Proposal uploaded for 1313 (coverpoint and bins expression resolution)

Hi Gord,

In general, does Verilog/SysV LRM states anywhere
that there should be a warning if the rhs of a
variable assignment is out of range of lhs?
I believe this behavior is mostly implementation
defined. 
So, while I agree with the proposal regarding the
way the type is determined for bin value
expression, generation of warning may not be
absolutely necessary.

Thx,
Swapnajit. 

>-----Original Message-----
>From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On 
>Behalf Of Gordon Vreugdenhil
>Sent: Tuesday, May 09, 2006 8:27 PM
>To: SV_EC List
>Subject: [sv-ec] Proposal uploaded for 1313 (coverpoint and 
>bins expression resolution)
>
>I've uploaded a proposal for Mantis 1313 ("No definition for 
>coverpoint and bin expression type rules").
>
>http://www.eda.org/svdb/bug_view_page.php?bug_id=0001313
>
>Note that part of what the proposal effectively says that if a 
>bins value is outside the representable range of the 
>coverpoint expression then a warning is generated and the 
>value used for the expression is implementation defined.  I 
>could set up rules for what the expression should be in such 
>cases but I don't feel too strongly about codifying that.  If 
>the consesnsus is that we should codify that part as well, I 
>can add something about that.
>
>Gord.
>--
>--------------------------------------------------------------------
>Gordon Vreugdenhil                                503-685-0808
>Model Technology (Mentor Graphics)                gordonv@model.com
>