[sv-ec] static initialization order fiasco

So is this a problem with classes in SystemVerilog like it is with C++ ?

 

This is that bummer where A's constructor references B, where A and B
are defined in different files and so their construction order is
indeterminate.  If B is constructed first, no problem, if not, ka boom.
Worse yet, it might work at first, but then fail when something/someone
unrelated changes the construction order.

 

I was wondering if there were some initialization differences in Verilog
that may have possibly eliminated this problem?

 

It seems like it could be much worse with SystemVerilog than C++ since
any object declared in a module and constructed in time zero is very
much like a static object constructed in C++, yes ?  Maybe even more so
since we like to 'netlist' even our testbench components together at
time zero.

 

And what about virtual interfaces ?  Could a class with an interface
argument to its constructor possibly be constructed before the interface
and be left with a null interface pointer? I assume also that the same
thing occurs with class pointers that are passed in as constructor
arguments.

 

What's the recommended solution ?  Same as C++, or just strip down the
constructors, or ???

 

Thanks

Tom Symons