[sv-ec] SystemVerilog enhancement requests - XtremeEDA

<forwarding bounced email from Hans van der Schoot>

-------- Original Message --------

Subject: SystemVerilog enhancement requests
Date: Wed, 29 Mar 2006 08:28:01 -0500
From: "Hans van der Schoot" <hvdschoot@xtreme-eda.com>
To: <sv-ec@server.eda.org>

To whom it may concern,

We have identified a few SystemVerilog enhancement requests within our
organization (XtremeEDA). I am not sure whether this is the right forum
to submit these to, but not knowing where else to go, here they are for
your consideration:

(1) Relieving the restriction that when individual array elements are
constrained, the index expression must be a literal constant (from LRM
section 13.3).

Consider the following constraint block, where foo not a constant
literal, such as some other rand class property:

   constraint c {
        foreach ( some_array, i ) {
            if ( i == foo ) {
               bar == some_array[i];
            }
        }
   }

Ideally, I would like to be able to write this as

  constraint c {
     bar == some_array[foo];
   }


(2) Task/function name overloading, i.e. the ability to define 2 methods
with the same name but with different formal argument lists.

    class myclass;
        task display( string s );
            $display( " string is %s ", s );
        endtask
        task display( integer i );
            $display(" Index is %d", i );
        endtask
    endclass

(3) Ability to query individual coverage bins of a coverage group at run
time.

Kind regards,
Hans van der Schoot


Hans van der Schoot, PhD
VP Engineering
XtremeEDA - ASIC Professional Services
613.324.2096 (Mobile)
hvdschoot@xtreme-eda.com
www.xtreme-eda.com