Date: Tue Mar 21 2006 - 01:11:44 PST
These come from a Tansmeta paper called "A SystemVerilog Testbench for Verifying a SIMD Processor": * The 'dist' operator in constraints does not have a 'default' option which is painful at times, e.g.: if 'a' is an integer there is no easy way to say "generate values of 'a' such that 5, 10, 15 occur twice the number of times any other value occurs". The syntax can be: a dist {5:=2; 10:=2; 15:=2; default:=1}; * Semaphore timeout option * Value Change Alerts Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
