[sv-ec] RE: [sv-bc] Clocking blocks - discrepancies hard to resolve

<Forwarding email from Jonathan Bromley>

-------- Original Message --------

Subject: RE: [sv-bc] Clocking blocks - discrepancies hard to resolve
Date: Tue, 7 Feb 2006 17:14:43 -0000
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
To: "Rich, Dave" <Dave_Rich@mentor.com>, <sv-ec@server.eda.org>


Dave,

> Check out mantis 890 and see if the proposal clarifies things

Thanks for the pointer.  It's hard to
keep up with all the activity on Mantis without nearly
full-time involvement, and I had completely missed 890.

Unfortunately it's still unassigned and we still have at least
two conflicting implementations, so it means that for any
practical purposes we must regard clocking blocks as being
off-limits until a resolution is established and supported.

Time for me to mount a soap-box:  A clocking variable
has two distinct "ends" - the design signal it drives or
samples, and the clocking block variable that is sampled
or driven by a client program block.  (By the way, we are
sorely in need of unambiguous *names* for each end of a
clocking variable.)  The LRM description of clocking would
have been massively more lucid had it been defined in terms
of the sampling and driving semantics of these two ends
individually.  Instead, we are forced to infer this
information - at some cost of interpretive pain - from
the description that exists.  I am aware that others
disagree with me because such a description smacks too
much of enforcing an implementation, but I still hanker
after it.
-- 
Jonathan Bromley, Consultant

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