Re: [sv-ec] foreach iterates over unpacked arrays

Shalom,

I proposed the language I just quoted from P1800.6.9.1.f.  Yet the fact
remains, as noted in http://www.eda.org/sv-bc/hm/3601.html , that
SystemVerilog does not have truly multidimensional arrays.

-- Brad

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Tuesday, January 24, 2006 8:40 AM
To: Brad Pierce; sv-ec@eda.org
Subject: RE: [sv-ec] foreach iterates over unpacked arrays

Brad,

We've been through this before.

There are dozens of places in the LRM which refer to arrays as
multi-dimensional, including a number which contrast them to
one-dimensional.

Shalom


> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
> Behalf Of Brad Pierce
> Sent: Tuesday, January 24, 2006 6:10 PM
> To: sv-ec@eda.org
> Subject: Re: [sv-ec] foreach iterates over unpacked arrays
> 
> According to P1800.10.5.3, "The number of [foreach] loop
> variables must
> match the number of dimensions of the array variable. Empty
> loop
> variables can be used to indicate no iteration over that
> dimension of
> the array, and contiguous empty loop towards the end can be
> omitted.".
> 
> I'm not convinced there's a problem with this text.  But if
> there is,
> it's that it's talking about the dimensions of the array
> variable,
> instead of the dimensions of the array being iterated over.
> Recall that
> SystemVerilog does not have true multidimensional arrays, it
> has arrays
> of arrays.  As it says in P1800.6.9.1.f, "The type of the
> slowest
> varying dimension of a multidimensional array type is itself an
> array
> type."
> 
> -- Brad