RE: [sv-ec] 5.7 Array Assignment question

Steven,

It may be convenient to think of it as you say
("SystemVerilog doesn't really have multi-dimensional arrays; it has
arrays whose elements can themselves be arrays"), but the entire SV LRM,
from start to finish, describes arrays differently, as multi-dimensional
entities.

See, for example, the start of Clause 5.
Or 22.6, which says that "$dimensions shall return:
- The total number of dimensions in the array".

Do you then agree that my example should be legal, and that some of the
statements about "one-dimensional" arrays are incorrect (given that the
LRM describes arrays as multi-dimensional entities)?

Shalom


>-----Original Message-----
>From: Steven Sharp [mailto:sharp@cadence.com]
>Sent: Friday, November 11, 2005 1:53 AM
>To: Dave_Rich@mentor.com; sv-ec@eda.org; Bresticker, Shalom
>Subject: RE: [sv-ec] 5.7 Array Assignment question
>
>
>>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
>
>>5.8 says,
>>"A subroutine that accepts a one-dimensional fixed-size array
>can also
>>be passed a dynamic array of a compatible type of the same
>size."
>>
>>and
>>
>>"A subroutine that accepts a dynamic array can be passed a
>dynamic array
>>of a compatible type or a one-dimensional fixed-size array of
>a
>>compatible type"
>
>These are somewhat misleading unless you realize that the
>"compatible
>type" may itself be a dynamic or fixed-size array.
>
>
>>5.14 says,
>>"A queue is analogous to a one-dimensional unpacked array that
>>grows and shrinks automatically."
>
>All of this wording would get simpler if the text didn't refer
>to
>multi-dimensional arrays.  SystemVerilog doesn't really have
>multi-
>dimensional arrays; it has arrays whose elements can themselves
>be arrays (or dynamic arrays or queues or associative arrays).
>There
>would be no need to have awkward wording about one dimension of
>an
>array if there weren't text that incorrectly referred to arrays
>of
>arrays as arrays with multiple dimensions.
>
>Steven Sharp
>sharp@cadence.com