RE: [sv-ec] 5.7 Array Assignment question

If so, this may be several errata, because there are several mentions in
the LRM of these one-dimensional arrays.

Shalom


>-----Original Message-----
>From: Rich, Dave [mailto:Dave_Rich@mentor.com]
>Sent: Wednesday, November 09, 2005 6:44 PM
>To: Bresticker, Shalom; sv-ec@eda.org
>Subject: RE: [sv-ec] 5.7 Array Assignment question
>
>This is a vestige of Vera. I remember someone telling me that
>Vera had
>only just introduced multi-dimensional arrays at about the same
>time the
>language was being donated to SystemVerilog.
>
>Remember, Verilog did not have multi-dimensional arrays in
>until V2001.
>Nor did it have even 1-dimentional arrays of wires. This made
>writing
>testbench interfaces very cumbersome. How did we survive! :)
>
>But I digress. This should be an errata.
>
>Dave
>
>
>> -----Original Message-----
>> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
>Behalf Of
>> Bresticker, Shalom
>> Sent: Wednesday, November 09, 2005 8:07 AM
>> To: sv-ec@eda.org
>> Subject: [sv-ec] 5.7 Array Assignment question
>>
>> 5.7 says,
>> " A dynamic array or a one-dimensional fixed-size array can
>be
>assigned to
>> a dynamic array of a compatible type."
>>
>> Why only a 1-dimensional fixed-size array?
>>
>> For example, why can't I write
>>
>> typedef int a[1:10];
>> a dyn[] ;
>> int b[1:5][1:10] ;
>>
>> dyn = b ;
>>
>> Shalom Bresticker
>> Intel Jerusalem LAD DA
>> +972 2 589-6852