[sv-ec] final block scheduling

From: Clifford E. Cummings <cliffc_at_.....>
Date: Fri Aug 26 2005 - 17:08:02 PDT
Hi, All -

I have attached a final block example that I have run on ModelSim. I don't 
think it is working yet on VCS (forgive me if this is a mis-representation).

The example did not work as I expected.

10.7 Final blocks
The final block is like an initial block, defining a procedural block of 
statements, except that it occurs at the
end of simulation time and executes without delays. A final block is 
typically used to display statistical information
about the simulation.


Based on this definition, I thought I could put $strobe commands into a 
final block and have the strobes execute before simulation finished.

Gord and I have exchanged email messages on this and he believes the final 
block should execute in the Reactive region(s), and complete the $finish 
before the $strobes can execute in the postponed region. I wanted to see 
the $strobed results too since I frequently $strobe final simulation 
results (then do a #1 $finish; - I have always hated the #1 in front of the 
$finish and I thought the final block could get me away from this ugly 
extra delay).

Opinions? The final block can have any command currently legal in a 
function, but if $strobe is never executed in a final block, then it should 
be an error to avoid final-block-usage confusion.

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


Received on Fri Aug 26 17:08:14 2005

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