FYI... from non-member submission... -----Original Message----- From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] Sent: Wednesday, June 01, 2005 8:43 AM To: sv-ec-approval@eda.org Subject: BOUNCE sv-ec@eda.org: Non-member submission from ["Joseph Bauer" <jbauer@denalisoft.com>] From: "Joseph Bauer" <jbauer@denalisoft.com> To: <sv-ec@server.eda.org> This is a multi-part message in MIME format. ------_=_NextPart_001_01C566C1.20BBBA4F Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, I've been working as an early adopter of System Verilog for the last few months leveraging a beta release of a simulator and will be using System Verilog as the backbone for functional verification of our production chip. I'm looking for additional resources (beyond the EDA's support team) such as a users group forum, open database of simple examples, ... Also I'm hoping to stay current with changes and updates to the System Verilog standard. I'd appreciate it if you can point me in the right direction on either of these requests. Best regards, Joe Bauer ------_=_NextPart_001_01C566C1.20BBBA4F Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable <html xmlns:o=3D"urn:schemas-microsoft-com:office:office" = xmlns:w=3D"urn:schemas-microsoft-com:office:word" = xmlns=3D"http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv=3DContent-Type content=3D"text/html; = charset=3Dus-ascii"> <meta name=3DGenerator content=3D"Microsoft Word 11 (filtered medium)"> <style> <!-- /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0in; margin-bottom:.0001pt; font-size:12.0pt; font-family:"Times New Roman";} a:link, span.MsoHyperlink {color:blue; text-decoration:underline;} a:visited, span.MsoHyperlinkFollowed {color:purple; text-decoration:underline;} span.EmailStyle17 {mso-style-type:personal-compose; font-family:Arial; color:windowtext;} @page Section1 {size:8.5in 11.0in; margin:1.0in 1.25in 1.0in 1.25in;} div.Section1 {page:Section1;} --> </style> </head> <body lang=3DEN-US link=3Dblue vlink=3Dpurple> <div class=3DSection1> <p class=3DMsoNormal><font size=3D2 face=3DArial><span = style=3D'font-size:10.0pt; font-family:Arial'>Hi,<o:p></o:p></span></font></p> <p class=3DMsoNormal><font size=3D2 face=3DArial><span = style=3D'font-size:10.0pt; font-family:Arial'>I’ve been working as an early adopter of System Verilog for the last few months leveraging a beta release of a simulator = and will be using System Verilog as the backbone for functional verification = of our production chip. I’m looking for additional resources = (beyond the EDA’s support team) such as a users group forum, open database of = simple examples, … Also I’m hoping to stay current with = changes and updates to the System Verilog standard. I’d appreciate it if = you can point me in the right direction on either of these = requests.<o:p></o:p></span></font></p> <p class=3DMsoNormal><font size=3D2 face=3DArial><span = style=3D'font-size:10.0pt; font-family:Arial'>Best regards,<o:p></o:p></span></font></p> <p class=3DMsoNormal><font size=3D2 face=3DArial><span = style=3D'font-size:10.0pt; font-family:Arial'>Joe Bauer<o:p></o:p></span></font></p> </div> </body> </html> ------_=_NextPart_001_01C566C1.20BBBA4F--Received on Wed Jun 1 15:38:42 2005
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