[sv-ec] Query on Interface

As the LRM tells that interfaces can be use for the purpose, Design as well
as verification ...

 

   So now in the example:

 

   The DUT is verified .The different values r given to the DUT through the
Interface's tasks from the top module.

 


	
		 
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 


According to the LRM(3.1a) 19.6.3 The interface for the above model should
like :

 

interface intf(input bit clk);

 

logic [0 :31] addr;

logic [0 : 31] data_in;

logic ready;

logic [0 : 31] data_out;

 

modport channel( input data_out,ready , output data_in,addr,clk,

                 import task initialize(input [0 : 31] addr_in,input [0 :
31] data),

                 import task write(input [0 : 31] data),

                 import task read(),

                 import task control(input [0 : 31] addr_in,input [0 : 31]
data));

 

task initialize;

input [0 : 31] addr_in;

input [0 : 31] data;

........

..........

..........

endtask

 

task control;

input [0 : 31] addr_in;

input [0 : 31] data;

........

..........

..........

endtask

 

 

task write;

input [0 : 31] data;

........

..........

..........

endtask

 

 

task read;

........

..........

..........

endtask

 

endinterface

 

 

So, as per the block diagram the top module from where, I want to use the
interface's tasks for forcing the value to the DUT, then :

 

 

Module top;

 

intf intf1(

           .clk(clk)

          );

 

//<<  How should I use the task...>>

 

/*

intf1.initialize(32'h0,32'h0); 

intf1.control(32'h0000003F,32'h0);               

               or

intf1.channel.control(32'h0000003F,32'h0);

intf1.channel.initialize(32'h0,32'h0);

*/

 

endmodule

 

 

 

   So, wht's the proper way to use the interface task in the top module for
forcing the value , with modport??

 

Regards

-Saurabh



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