Re: [sv-ec] Scheduling cycle

I agree -- given that functions and tasks can be impure,
surprising things can happen.

The basic questions are "how surprising" are the things that
can happen and are there parallels to Verilog scheduling
that should be semantically consistent.  I think that is
what everyone is trying to deal with.  It is clear we won't
end up with a "no holes exist" approach, but if we can make
some clear parallels, things might be both more explainable
and less surprising in practice.

Gord


Steven Sharp wrote:

> In general, I don't think it will be possible to have programs calling
> module tasks/functions without doing something that will surprise
> someone.  Ultimately the user will need to understand how it is defined,
> which is easier if the definition is simple.  So there is a trade-off
> between trying to minimize the chance of a surprise, and trying to keep
> the definition simple so that the user understands when they will get
> that surprise and why.
> 
> Steven Sharp
> sharp@cadence.com
> 

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Gordon Vreugdenhil,  Staff Engineer               503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com