Re: [sv-ec] Clocking Blocks

Thanks for the clarification.

Swapnajit.

Arturo Salz wrote:
> 
> Swapnajit,
> 
> Your understanding is correct. In each of your examples
> there are four signals: in1, o1, cb.in1, cb.o1. Of these, the
> only the signals inside the scope of the clocking block are
> subjected to the clocking block's sampling/drive semantics,
> and those are cb.in1 and cb.o1.
> 
>     Arturo
> 
> ----- Original Message -----
> From: "Swapnajit Chakraborti" <swapnaj@cadence.com>
> To: <sv-ec@eda.org>
> Sent: Friday, February 18, 2005 5:54 AM
> Subject: [sv-ec] Clocking Blocks
> 
> > I have a small doubt regarding how to use
> > clocking blocks.
> >
> > Is it correct that only declaring a clocking
> > block does not impact timings of sampling/drive of
> > the signals declared inside it (See Example 1)?
> > We need to prepend the clocking block name with
> > the signal (see Example 2) in order to see the
> > synchronization and timing impact.
> >
> >
> > Example 1:
> > ----------
> >
> > module m1;
> >    ...
> >
> >    clocking cb @(posedge clk);
> >     input #2 in1;
> >     output #2 o1;
> >    endclocking
> >
> >    ...
> >    always @ (posedge clk)
> >    begin
> >       // No impact due to clocking block? Value of "o1" at
> >       // posedge clk.
> >       if (o1 != 1'b00)
> >       ...
> >    end
> >    ...
> >
> > endmodule
> >
> >
> > Example 2:
> > ----------
> >
> > module m1;
> >    ....
> >
> >    clocking cb @(posedge clk);
> >     input #2 i1;
> >     output #2 o1;
> >    endclocking
> >
> >    ...
> >    always @ (posedge clk)
> >    begin
> >       // Impact due to clocking block? Value of "o1" driven
> >       // after 2 timesteps from posedge clk.
> >       if (cb.o1 != 1'b00)
> >       ...
> >    end
> >    ...
> >
> > endmodule
> >
> >
> > Although, it is somewhat clear from the examples in LRM, I didn't
> > find it explicitly mentioned anywhere.
> >
> > Thx,
> > Swapnajit.
> >