[sv-ec] Clocking Blocks

I have a small doubt regarding how to use
clocking blocks.

Is it correct that only declaring a clocking
block does not impact timings of sampling/drive of
the signals declared inside it (See Example 1)? 
We need to prepend the clocking block name with
the signal (see Example 2) in order to see the
synchronization and timing impact.


Example 1:
----------

module m1;
   ...

   clocking cb @(posedge clk);
    input #2 in1;
    output #2 o1;
   endclocking

   ...
   always @ (posedge clk)
   begin
      // No impact due to clocking block? Value of "o1" at
      // posedge clk.
      if (o1 != 1'b00)    
      ...
   end
   ...

endmodule


Example 2:
----------

module m1;
   ....

   clocking cb @(posedge clk);
    input #2 i1;
    output #2 o1;
   endclocking

   ...
   always @ (posedge clk)
   begin
      // Impact due to clocking block? Value of "o1" driven
      // after 2 timesteps from posedge clk.
      if (cb.o1 != 1'b00)    
      ...
   end
   ...

endmodule


Although, it is somewhat clear from the examples in LRM, I didn't
find it explicitly mentioned anywhere.

Thx,
Swapnajit.