[sv-ec] Writes to program ports and continuous assignments

Hi can someone help me answer some questions?

Is the output port of program block considered a program variable or a design variable if it is connected to a module? I would think the rule to prevent blocking assignments to design variables should prevail, but can't find any mention of it. The same question goes for continuous assignments to design variables. If I use a blocking assignment to assign the RHS of a cont. assign that assigns a design variable, I have broken the race-free guarantee of the program block

module design(input int A);

int B,C;

endmodule

program testbench(output int A);

int B;

assign top.DUT.B = B;

initial begin
        #1
        A=1;
      B=2;
        top.DUT.C <= 3;
      end
endprogram

module top;
int A;
design DUT(A);
testbench TB(A);
endmodule

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625
Received on Tue Dec 14 09:44:19 2004