[sv-ec] sv-ec ballot

Hi Mehdi,
Sorry for the delay in voting. Last night, my internet connection got
busted. Below are my votes.

Errata

7 Clarification to 20.4.1, new 20.10
__X__ Yes ____ No

8 Randsequence grammar issues
__X__ Yes ____ No

173 Is the order of declaration in a covergroup
__X__ Yes ____ No

197 Is a String an array
__X__ Yes ____ No

203 Section 3.7, delete the sentence "and embedded null bytes are included"
__X__ Yes ____ No

231 Clarify the second paragraph in Section 16.5
__X__ Yes ____ No

236 Behavior of the cycle_delay with 'Zero' value
_X___ Yes ____ No

238 Pipelined value access in clocking block
____ Yes __X__ No
The intended functionality is already available via $past system call.

240 Expression evaluation with cycle_delay
____ Yes __X__ No

The semantics of the suggested solution are incompletely specified. It
seems to impose complex semantics of parallelism within Verilog expression.

**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
**********************************************
Received on Fri Oct 8 07:13:59 2004