RE: [sv-ec] Errata 238 and 240 and a suggestion for a BNF change

 
First, just to clarify, we are suggesting to have sequence_expr
everywhere under
testbench ( 'program' construct ) layer. We are not suggesting to have
those in the design layer. Does it help to remove your concern?

Such functionality to handle the cycle-delayed expression is available
in
today's HVL (e.g. Jeda ), and we found it's the basic mechanism to
construct
effective self-checking testbenches. Just having it under 'assertion'
makes the langage
insufficient for general purpose testbench systems required for various
design types.

Second, we don't see any issues of having delay on expression
evaluation. We think the reason why a function couldn't have delay in
Verilog (1995) is due to the static allocation of variables in the
original Verilog implementation. SystemVerilog allows 'automatic'
variables and arguments, so the variable space issue (in the case of
reentrant call) should not be the problem. We can put the semantic
restriction to only allow the delay in the auto function.
 
We believe we are designing SystemVerilog as a general purpose system
design language
for the next generation, and having such a flexible mechanism is
extremely important
for that. It should not be restricted just because the old
implementation could
not handle it.

-Eugene

On Oct 4, 2004, at 1:57 PM, eugene zhang wrote:

>
>
> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Monday, October 04, 2004 1:47 PM
> To: sv-ec@eda.org; Surrendra.Dudani@synopsys.com
> Subject: RE: [sv-ec] Errata 238 and 240 and a suggestion for a BNF
> change
>
>
> If the suggestion is that sequences can be used in arbitrary
> SystemVerilog expressions, then Surrendra is right to be concerned.
>
> Verilog expressions are assumed to be evaluated "instantly", with no
> passage of simulation time. Function calls are not allowed to have
> delays for this reason. There are good reasons for this, and trying
> to change it would have major impact on the language. Every context
> where expressions can be used would have to be considered and possibly

> have its semantics redefined. This would require a lot of work, and
> cannot be done lightly.
>
> Steven Sharp
> sharp@cadence.com
>
>
>
>
>
>
>

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com]
Sent: Monday, October 04, 2004 1:47 PM
To: sv-ec@eda.org; Surrendra.Dudani@synopsys.com
Subject: RE: [sv-ec] Errata 238 and 240 and a suggestion for a BNF
change

If the suggestion is that sequences can be used in arbitrary
SystemVerilog expressions, then Surrendra is right to be concerned.

Verilog expressions are assumed to be evaluated "instantly", with no
passage of simulation time. Function calls are not allowed to have
delays for this reason. There are good reasons for this, and trying to
change it would have major impact on the language. Every context where
expressions can be used would have to be considered and possibly have
its semantics redefined. This would require a lot of work, and cannot
be done lightly.

Steven Sharp
sharp@cadence.com
Received on Tue Oct 5 00:16:16 2004