The following suggestion is a follow-up to the discussion in the last sv-ec meeting on Errata 238 ( Pipelined value access in clocking block) and
Errata 240 ( Expression valuation in cycle delay), with comments from Arturo.
In summary, 238 and 240 should be replaced by this proposal. as you can see, the change is minimal, however it can bring benefits to users. From our
experiences, writing self-checking testbenches, with embedded assertions, is a natural process. Checking is usually done in testbench, doesn't
have to be in code called "Assertions' only.
We'd like to hear your feedback, tells us why if you say no and try to convince us. If we agree, the goal is to put this into the first IEEE standard.
Below is a brief description:
We carefully examined the whole section 17, and found that the functions we requested on SV-EC 238 (Pipelined value access) and 240 (delayed expression) can also be realized with 'sequence_expr' and $past system tasks in section 17 Assertions.
We agree that the basic functionality can be somewhat achieved by using 17.16 (expect statement), but in terms of the flexibility, we still suggest to have 'sequence_expr' as a part of regular expression.
This provides an extremely flexible mechanism to express the cycled sequences anywhere in the program statement. For example, it can be used in the conditional qualifier for 'if' and 'while' statements .
Given that the the assertion mechanism must be implemented, we don't see any major technical difficulty to include it as a part of the primary. This extension raises the SystemVerilog's expression capability to a totally different level.
Suggested Revised BNF: to add sequence_expre to primary
<?/x-tad-bigger><?/fontfamily><?/smaller><?fontfamily><?param Times New Roman><?bigger> A.8.4 Primaries
primary ::=
.
.
sequence_expr
<?/bigger><?/fontfamily><?smaller>
Cheers,
-Eugene
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