[sv-ec] [SystemVerilog Errata 0000004]: Add rs_rule precedence and example in Section 12.16

A BUGNOTE has been added to this bug.
======================================================================
http://www.eda.org/svdb/bug_view_page.php?bug_id=0000004
======================================================================
Reported By: dwsmith
Assigned To: Ray_Ryan
======================================================================
Project: SystemVerilog Errata
Bug ID: 4
Category: SV-EC
Reproducibility: always
Severity: feature
Priority: immediate
Status: assigned
Type: Errata
======================================================================
Date Submitted: 06-02-2004 14:09 BST
Last Modified: 08-27-2004 15:27 BST
======================================================================
Summary: Add rs_rule precedence and example in Section 12.16
Description:
http://www.eda.org/sv-ec/hm/1830.html
======================================================================

----------------------------------------------------------------------
 Ray_Ryan - 08-27-2004 15:27 BST
----------------------------------------------------------------------
The problem here is the precedence of ':=' relative to '|'. To achieve the
desired semantics, ':= should have higher precedenc that '|'.

Proposal:
Modify Table 7-2 (in section 7.9) to move ':=' and ':/' from the
2nd to the last (lowest) entry and insert them between the 1st two
entries (just above the entry for '|'). The table is then:

------------------------------------------------------------------
| () [] :: . | left |
| := :/ | none |
| + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) | right |
| ** | left |
| * / % | left |
| + - (binary) | left |
| << >> <<< >>> | left |
| < <= > >= inside dist | left |
| == != === !== =?= !?= | left |
| & (binary) | left |
| ^ ~^ ^~ (binary) | left |
| | (binary) | left |
| && | left |
| || | left |
| ?: (conditional operator) | right |
| –> | right |
| = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= <= | none |
| {} {{}} | concatenation |
------------------------------------------------------------------

Add the following text and example at the end of section 12.16.1.

Note that the := operator has higher precedence than the '|' operator. The
implication of this is illustrated in the following example:

  randsequence
    main : first second third;
    first : add | sub;
    second : push := x | y | pop;
    ...
  endsequence

In this example, the production 'second' contains three choices,
"push := x", "y" and "pop". The weight of the "push" option is specified
by the variable "x". The weight of the other two option defaults to the
value 1. In order to use the bit-wise inclusive OR operator '|' in a
weight expression parenthesis are needed as in:

  randsequence
    main : first second third;
    first : add | sub;
    second : push := ( x | y ) | pop;
    ...
  endsequence

Here the production 'second' contains two choices, "push := (x | y)" and
"pop". The weight of the first choice is the value of the expression
('x' inclusive OR 'y').

Bug History
Date Modified Username Field Change
======================================================================
06-02-04 14:09 dwsmith New Bug
06-02-04 14:10 dwsmith Assigned To => Ray_Ryan
06-02-04 14:10 dwsmith Status new => assigned
06-03-04 15:35 sv-ec Bug Monitored: sv-ec
06-03-04 15:41 dwsmith Description Updated
08-06-04 10:58 pieper Priority normal => immediate
08-06-04 10:58 pieper Type => Errata
08-27-04 15:27 Ray_Ryan Bugnote Added: 0000044
======================================================================
Received on Fri Aug 27 15:27:47 2004