[sv-ec] [SystemVerilog Errata 0000004]: Add rs_rule precedence and example in Section 12.16

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http://www.eda.org/svdb/bug_view_page.php?bug_id=0000004
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Reported By: dwsmith
Assigned To: Ray_Ryan
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Project: SystemVerilog Errata
Bug ID: 4
Category: SV-EC
Reproducibility: always
Severity: feature
Priority: immediate
Status: assigned
Type: Errata
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Date Submitted: 06-02-2004 14:09 BST
Last Modified: 08-06-2004 10:58 BST
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Summary: Add rs_rule precedence and example in Section 12.16
Description:
http://www.eda.org/sv-ec/hm/1830.html
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Bug History
Date Modified Username Field Change
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06-02-04 14:09 dwsmith New Bug
06-02-04 14:10 dwsmith Assigned To => Ray_Ryan
06-02-04 14:10 dwsmith Status new => assigned
06-03-04 15:35 sv-ec Bug Monitored: sv-ec
06-03-04 15:41 dwsmith Description Updated
08-06-04 10:58 pieper Priority normal => immediate
08-06-04 10:58 pieper Type => Errata
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Received on Fri Aug 6 10:58:42 2004